When the driver enable pin, DIR, is logic high, the differential outputs R2 and R1 follow the logic states at data input L2. A logic high at L2 causes R2 to turn high and R1 to turn low. In this case the differential output voltage defined as V_OD = V_R2 – V_R1 is positive. When L2 is low, the output states reverse: R1 turns high, R2 becomes low, and V_OD is negative.

When DIR is low, both outputs turn high-impedance. In this condition the logic state at L2 is irrelevant. The DIR pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The L2 pin has an internal pull-up resistor to V_IO, thus, when left open while the driver is enabled, output R2 turns high and R1 turns low.

Table 7-6 is valid for both half duplex and full duplex modes, and is independent of state of TERM_TX, TERM_RX and SLR pins.

In full duplex mode, if SHDN is high, receiver is always enabled. In half duplex mode, receiver is enabled is DIR = Low/floating and disabled if DIR = V_IO. When the differential input voltage defined as V_ID = V_R2 – V_R1 or V_R3 – V_R4 is higher than the positive input threshold, V_TH+, the receiver output, L2, turns high. When V_ID is lower than the negative input threshold, V_TH-, the receiver output, L2, turns low. If V_ID is between V_TH+ and V_TH- the output is indeterminate.

In half duplex mode, when DIR is high, the receiver output is high-impedance and the magnitude and polarity of V_ID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Table 7-7 is valid irrespective of state of TERM_TX, TERM_RX and SLR pins.