SPRUJB5 February   2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Input
      2. 2.3.2 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbutton
      4. 2.4.4 User Pushbutton And LEDs
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input/Output
      2. 2.5.2 DisplayPort and HDMI
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG and Emulation
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Module
      7. 2.5.7 UARTs for Terminal and Logging
      8. 2.5.8 USB Interfaces
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Camera Interface, 22-Pin Flex
      2. 2.6.2 Camera Interface, 40-Pin Expansion
      3. 2.6.3 CAN-Bus Interface
      4. 2.6.4 DSI Display Interface
      5. 2.6.5 OLDI/LVDS Display Interface
      6. 2.6.6 User Expansion Header
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 I2C Address Mapping
      3. 2.7.3 GPIO Mapping
      4. 2.7.4 I2C GPIO Expander Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Identification EEPROM
      7. 2.7.7 Memory and Storage
      8. 2.7.8 Power Distribution
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 Thermal Compliance
    2. 4.2 EMC, EMI, and ESD Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.6.4 DSI Display Interface

The EVM supports a 22-pin flex (0.5mm pitch) connector [J40] for interfacing with external display modules and panels. The interface provides MIPI DSI-2 interface (4 lanes), clock and control signals, and power (3.3V) to the panel. The DSI interface is shared and multiplexed between the 22-pin flex connectors and on-board DisplayPort transceiver. See Section 2.7.4 table for details on selection control.

Table 2-14 DSI Display Pin Definition [J40]
Pin # Pin Name Description Dir
1

Power

Power, 3.3V

Output

2

I2C_SDA

I2C Data (I2C1)

Bi-Dir

3

I2C_SCL

I2C Clock (I2C1)

Output

4

GND

Ground

5

GPIO1

GPIO, Undefined (See GPIO Table)

Bi-Dir

6

GPIO0

GPIO, Undefined (See GPIO Table)

Bi-Dir

7

GND

Ground

8

DSI0_D3_P

DSIPort 0 Data Lane 3

Input

9

DSI0_D3_N

DSIPort 0 Data Lane 3

Input

10

GND

Ground

11

DSI1_D2_P

DSIPort 0 Data Lane 2

Input

12

DSI1_D2_N

DSIPort 0 Data Lane 2

Input

13

GND

Ground

14

DSI0_CLK_P

DSIPort 0 CLK

Input

15

DSI0_CLK_N

DSIPort 0 CLK

Input

16

GND

Ground

17

DSI0_D1_P

DSIPort 0 Data Lane 1

Input

18

DSI0_D1_N

DSIPort 0 Data Lane 1

Input

19

GND

Ground

20

DSI0_D0_P

DSIPort 0 Data Lane 0

Input

21

DSI0_D0_N

DSIPort 0 Data Lane 0

Input

22

GND

Ground

Output
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